1. Field of the Invention
The present invention relates to a pipelined computer system, and in particular to an instruction code access control system used in a pipelined processor.
2. Description of Related Art
In the prior art, it has been conceived to process respective stages of instruction executions in parallel as simultaneously as possible, such as reading an decoding of instruction codes, address calculation, operand access. This is called a "pipelined processing".
In general, a processor adapted for the pipelined operation is such that instruction codes are accessed through an address bus or data bus common to operand data, and therefore, a reading of an instruction code from a memory is often conflicted with an operand access of a preceding instruction to be executed in parallel with the reading operation of instruction codes from the memory.
To resolve the conflict, it is an ordinary practice to collect memory access requests issued at respective stages of pipeline processing to a memory interface portion of a processor system, so that an associated arbiter selects one of the requests and causes to execute an asynchronous memory access at a timing unrelated to the pipelined operation.
In this method, it becomes required that the respective stages of the pipeline processing issuing a memory access request have a buffer mechanism for waiting or accumulating the data which has caused the memory access request. It is also necessary to adjust the lag between the timing of the pipeline processing and that of access data outputted in an asynchronous way. In this method, on the contrary, the operation cycle of pipeline processing is not subjected to any limit by a memory access period, differently from the method in which a memory access is controlled in a pipeline processing manner. Accordingly, this method has an advantage capable of improving the efficiency of the overall system through improving the efficiency of a pipeline processing.
Furthermore, it has been a general practice to provide a buffer mechanism called an "instruction queue" for a stable supply of an instruction code in pipelined manner, so that an instruction code is read out and stored in the instruction queue only when operand data access of the preceding instruction is not carried out. This instruction code accumulating manner means that the instruction code access is set at a degree of priority lower than that of the operand data access.
As a result, this method has such a disadvantage that the instruction queue can secure only an insufficient amount of instruction codes in the next two cases, that is,
(1) the case where the pipeline processing is resumed after the pipeline processing is discontinued and the instruction queue's content is cleared as the result of a conditional branch instruction, interrupt, or the like; and
(2) the case where the instruction code access is interrupted for a long period on account of the frequent occurrence of operand data access.
The above shortage of the instruction codes stored in the instruction queue connotes the possibility of impeding the pipeline operation.
In order to surmount the above defects, it is considered to enhance the priority of instruction code access higher than that of operand data access, when the instruction queue becomes short in instruction codes stored. However, if the period of higher priority of instruction code access becomes too long, the following problems will occur.
(1) a normal pipeline processing may be interrupted because the operand access required for execution of an instruction is prevented; and
(2) the amount of instruction codes having stored in the instruction queue invalidated at the time of branch, interrupt, or the like may be increased, and as a result the number of fruitless data access will increase. This problem will impede the efficiency improvement of the overall system, particularly where the time periods required for each stage of pipeline processing are improved in comparison to the time periods required for data access.